1. Field of Invention
The present invention relates methods for forming capacitors, and particularly to a method for forming a multilayer-electrode capacitor.
2. Description of Related Art
In semiconductor industries, there is a trend to increase the integration and to decrease the scale of semiconductor devices. However, decreasing the scale of a capacitor reduces the storage capacity thereof for electrical charges and leads to low capacitance. Therefore, a method to form capacitors with a high capacitance value and without increasing the size thereof is desired.
Capacitors can be divided into stacked capacitors and trench capacitors according to the production methods thereof. Stacked capacitors are formed on the dielectric layer on a device after finishing all features (such as transistors) and interconnecting lines. The production method for stacked capacitors is simpler and cheaper than that for trench capacitors. But because of the larger area occupied by capacitors on the device, the number of capacitors per unit area is smaller. Depositing several dielectric layers and conductive layers in a trench on a semiconductor substrate forms trench capacitors.
Multilayer electrodes have been developed as a way to achieve capacitors with larger capacitance values without increasing the area occupied by capacitors on the device. U.S. Pat. No. 6,261,895 describes a process for the formation of capacitors having multilayer electrodes for increasing capacitance values. However, conventional methods for forming multilayer electrode capacitors have some drawbacks. For example, FIG. 1A shows a cross-sectional view of a multilayer electrode capacitor. The conventional method for forming the capacitor in FIG. 1A includes following steps: forming a trench in a substrate 102; depositing a first metal layer 104, a first polysilicon layer 106, a first dielectric layer 108, a second polysilicon layer 110, a second metal layer 112, a third polysilicon layer 114, a second dielectric layer 116 and the fourth polysilicon layer 118 on the inner surface of the trench in sequence; depositing a third metal layer 120 on the fourth polysilicon layer 118 to fill the trench; and performing a CMP (chemical-mechanical planarization) process to expose the first metal layer 104. The multilayer structure illustrated in FIG. 1A is thus achieved. FIG. 1B shows a top view of the capacitor in FIG. 1A.
Reference is now made to FIG. 1C. After finishing the structure shown in FIG. 1A, leads 128, 126, 124 and 122 are formed on the exposed surface of the first metal layer 104, the second metal layer 112 and the third metal layer 120 by photolithography. The first metal layer 104 and the third metal layer 120 are connected to an electrode by leads 128, 124 and 122. The second metal layer 126 is connected to the other electrode by leads 126. Then, the first metal layer 104 and the second metal layer 112 can form a capacitor, and the second metal layer 112 and the third metal layer 120 form another capacitor. Therefore, the multilayer-electrode capacitor can increase capacitance value by enlarging the charge storage area in capacitors.
Unfortunately, the conventional multilayer electrode capacitor shown in FIG. 1A has some drawbacks with regard to making leads 128, 126, 124 and 122. Without increasing the area occupied by capacitors on the substrate, each layer formed on the inner surface of the trench has a thickness ranging from several nanometers to no more than a hundred angstroms (Å). Because of the thickness, the leads 122, 124, 126 and 128 cannot be formed on the thin metal layer precisely by the present lithography technology. Improper positioning of the leads causes many electrical defects, such as short circuits, electric leakage or loss of charge-storage capacity.
The prior art also discloses another method for connecting the metal layers in the convention multilayer electrode capacitor. Reference is made to FIG. 1D, in which the conductive layer 130 is used to connect electrically the first metal layer 104, the second metal layer 112 and the third metal layer 120 with the line 132 and overcomes the drawback of the leads made by photolithography. Although the three metal layers 104, 112, 120 are connected as an electrode, the capacitor can not be formed with only one electrode. Therefore, The capacitor shown in FIG. 1D has no function for electrical charge storage.